Authors: Christian Radici, Applications Engineer, Manchester. Jae Wei, Applications Engineer, Shanghai.

This interactive application note contains embedded Cloud based simulations to augment the text.

To open the embedded simulation, simply hover over the simulation image. Left click anywhere in the graphic area once the central play button changes in colour. This opens the schematic in the Cloud environment. See the interactive application note tutorial page for more details on how to use the simulations. See accompanying application note: AN50005.

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Introduction

In today's automotive and power industries, higher power requirements are leading to more designs that require lower R_DSon. Sometimes this is not achievable with a single packaged MOSFET and the design will need to make use of two or more devices in parallel. Higher power applications could also require the use of high performance substrates like heavy copper PCB, IMS (Insulated Metal Substrate) or DBC (Direct Bonded Copper) and even bare dies. By paralleling, the total current and thus dissipation is shared between each device. However, this is not as simple as applying Kirchhoff's current law: MOSFETs are not identical and thus they don't share equally.

This interactive application note describes how sharing imbalances between paralleled MOSFETs form as well as guidelines and tools to take them into account. The final goal is to provide a set of best practices that can help to design circuits with standard paralleled MOSFETs.

Applications

Applications that require paralleled MOSFETs can be categorized into two main groups depending on the operation of the MOSFET: switch-mode and load switch. The switch-mode types include motor drive applications, such as belt starter generators and superchargers, braking regeneration systems and switched mode power converters, such as regulators (DC/DC) and other types of inverters (DC/AC). Here the half-bridge represents the fundamental cell block that all the major circuit topologies are based upon. The MOSFETs are generally required to switch ON and OFF at a constant rate that can vary widely depending on the application, and are driven by a rectangular pulse with varying duty cycle (PWM). This is done with the intent of modulating the output power of the system to the load.

Load switching mainly refers to applications where MOSFETs are used in series with the battery such as in activation, safety switches and e-fuses, one example being battery isolation switches. The MOSFETs are required to switch ON once and will remain fully ON until the system is switched OFF. They might be swiftly switched OFF only in case some type of failure has been detected, for example in case of short circuit. Additionally, these switches may come in a back-to-back configuration in order to offer an additional reverse polarity protection.

This interactive application note focuses on switch-mode applications and the half-bridge configuration.

Key specifications

The most important figure to monitor is the MOSFET junction temperature. This is a function of the power dissipated in each device which ideally should be uniform for all paralleled MOSFETs. Since P = V × I and the same voltage is applied across all the paralleled MOSFETs, it is clear that for ideal operation the current should be shared equally by each MOSFET and this is the simplest metric to quantify how well the MOSFETs perform. However, an equally valid approach is to consider the dissipated energy (or power), as done throughout the majority of this application note. Current sharing in paralleled MOSFETs is mainly affected by the part to part variation of three data sheet parameters: R_DSon, Q_G(tot), and V_GS(th).

Simulation 1 - Paralleled MOSFETs: ideal case

The circuit used in simulation 1 is composed of 3 MOSFETs in parallel both at the high-side and low-side driving an inductive load.

The simulation setup is as follows:

• Part name: BUK7S1R0-40H N-channel 40 V, 1.0 mΩ standard level MOSFET in LFPAK88
• V_SUPPLY = 12 V
• f_SW = 20 kHz
• DC = 50%
• V_GS = 15 V
•  I_LOAD = 150 A
• L_LOAD = 4 µH

Each MOSFET is conducting a current of 50 A, which is set by the constant current source of 150 A used in series with the load inductor. Parasitic inductance linked to the layout has been added to the simulation. There is no difference in terms of parasitics between the three branches (each branch corresponds to a single MOSFET and the path connecting it to the others in parallel through inlet and outlet: V_SUPPLY and phase for the high-side, phase and GND for the low-side).

Simulation 1 - Paralleled MOSFETs: ideal case

MOSFET dissipation and parameters' influence on current sharing

Power dissipation in a MOSFET employed in a half-bridge is caused by two processes: conduction and switching. Fig. 1 shows the current flowing through the paralleled MOSFETs in case of ideal devices and the dissipated energy. There is no hard separation between switching and conduction losses. However, in a simulation environment, the dissipated power can help in detecting this separation.

Figure 1. MOSFETs drain current (I_D) and energy dissipation (E_diss) - ideal case

Fig. 2 shows how the turn-ON phase has been found: the first point is set at around 9.9 μs where the power is 0 W, the second point is set at 10.4 μs where the dissipated power is almost constant at around 1.8 W (dissipated power during conduction - P_cond). The drain current (I_D) flowing through MOSFET M1 is shown in Fig. 2, the drain-to-source voltage (V_DS) across it rises before the current falls, hence the valid loss recorded here. Moreover, the increase in dissipated power starting at 10 μs and lasting around 100 ns is due to the gate charge required to turn-ON the device.

Figure 2. MOSFETs drain current (I_D), energy dissipation (E_diss) and power dissipation (P_diss) - ideal case: equal MOSFETs. The turn-ON phase is indicated

Fig. 3 shows how the turn-OFF phase has been found: the first point is set at 36.2 μs where the power is 0 W, the second point is set at around 35.2 μs where the dissipated power starts to increase from 1.8 W.

Figure 3. MOSFETs drain current (I_D), energy dissipation (E_diss) and power dissipation (P_diss) - ideal case: equal MOSFETs. The turn-OFF phase is indicated

Equation 1 expresses the power dissipation in the MOSFET, while equations 2 and 3 show the individual contributions from switching and conduction.

(Eq. 1)  

(Eq. 2)  

(Eq. 3)  

Where E_sw(ON) and E_sw(OFF) are the energy dissipation during turn-ON and turn-OFF, E_cond is the energy dissipation during a single conduction phase and fsw the switching frequency. In this case, the total average power dissipated across each MOSFET over one cycle is around 2.1 W at 20 kHz.

Table 1 shows the energy calculated during switching (divided into ON and OFF) and conduction. The degree of sharing of each MOSFET can be defined in several ways. Here it is defined as ratio between the energy dissipated in one MOSFET and the total energy dissipated in all of the paralleled devices, by using equation 4.

(Eq. 4)  

In this case, switching (E_sw(ON) + E_sw(OFF)) accounts for around 55 % of the overall dissipation. However the switching:conduction dissipation ratio will depend on the switching frequency: a low frequency will lead to conduction losses dominating whereas switching losses will dominate at high frequency. Therefore, in order to simplify the evaluation, one might consider to take into account only parameters influencing the most important contribution.

With the MOSFET fully ON the only source of dissipation is given by its drain-to-source on state resistance (R_DSon). On the other hand, switching depends on threshold voltage (V_GS(th)) and input charge (Q_G(tot)).

Influence of parameter spread on current sharing performance

As previously mentioned, manufacturing spreads in data sheet parameters have a big impact on current sharing. Spread refers to the difference between maximum and minimum of a certain parameter. These spreads are unavoidable and caused by both intra- and inter- wafer variation during the silicon die fabrication. Every MOSFET produced by any manufacturer will carry these spreads. Nexperia’s power MOSFET fabrication processes are optimised to keep spreads as tight as possible in order to achieve good performance and reliability.

Static operation (DC): drain-source on-state resistance

Fig 3. shows the BUK7S1R0 R_DSon data sheet values.

Figure 3 BUK7S1R0-40H data sheet characteristics: R_DSon

The total spread, as per data sheet, is ΔR_DSon = 0.38 mΩ or ΔR_DSon,rel = ± 21.6 % (relative percentage with respect to the nominal value).

Simulation 2 -  Paralleled MOSFETs: R_DSon spread

The MOSFET having lower R_DSon (M1) will need to handle more energy, vice versa for M3. Both sharing during conduction and switching are impacted. M1 is now dissipating 2.5 W, around 20% more than the ideal case (2.1 W) while M3 is dissipating 1.7 W. These results are valid only for the first cycles of operation, after which the temperature dependency of the R_DSon partly balance out the sharing, more information is provided in the corresponding section on temperature dependency.

Simulation 2 -  Paralleled MOSFETs: R_DSon spread

Simulation 3 - Paralleled MOSFETs: Q_G(tot) spread

The simulation setup and results are summarized in Table 3. At turn-ON the device with lower input capacitance (M1) will switch ON first thus handling majority of the current. On the other hand, at turn-OFF the MOSFET with higher input capacitance (M3) will switch OFF last now handling most of the current. The sharing during switching is the most impacted, while conduction has changed only marginally. M3 is now dissipating 2.8 W (0.7 W more than the ideal case) while M1 is dissipating 1.9 W.

Simulation 3 - Paralleled MOSFETs: Q_G(tot) spread

Dynamic operation: gate-source threshold voltage – V_GS(th)

Fig 4 shows the data sheet values for gate-source threshold voltage.

Figure 4. BUK7S1R0-40H data sheet characteristics: gate-source threshold voltage

The total spread, as per data sheet, is ΔV_GS(th) = 1.2 V or ΔV_GS(th)rel = ±20 %.

Simulation 4 - Paralleled MOSFETs: V_GS(th)data sheet spread

The simulation setup and results are summarized in Table 3. The MOSFET having lower V_GS(th) will need to handle more energy overall. At turn-ON M1 will switch ON first thus handling majority of the current. Moreover, at turn-OFF the same MOSFET will switch OFF last, again, handling most of the current. The sharing during switching is the most impacted, with one MOSFET (M3) participating only minimally in the process, while conduction has changed only marginally. M1 is now dissipating 4.7 W (2.6 W more than the ideal case) while M3 only 1 W.

Simulation 4 - Paralleled MOSFETs: V_GS(th) spread

In conclusion, the MOSFET having lower V_GS(th) will need to handle more energy both during turn-ON and turn-OFF, while with the capacitance spread the switching energy will be balanced between at least two devices. These results are valid only for the first cycles of operation, due to the temperature dependency of the V_GS(th). More information is provided in the corresponding section on temperature dependency.

Data sheet and batch spreads

If considering multiple MOSFETs in parallel, data sheet spreads may be too conservative. The design would certainly be reliable but the improved robustness to a wider worst case scenario could end up being more expensive. In this case then, the designer would prefer to evaluate a less stringent worst case scenario that, even if not guaranteed like the data sheet, can still be considered realistic. This is done by looking at batch spreads.

A batch refers to a group of devices that go through the whole manufacturing process at the same time. The number of dies in a batch can vary from a few thousands to over a few millions, depending on the size of the dies themselves. Within a set of paralleled MOSFETs, it is preferable to choose parts coming from the same reel in order to increase the possibility of using devices from the same batch. Furthermore, using MOSFETs with identical batch codes, which can be found on the package under the marking code, could be used to further narrow down the selection during PCB assembly.

Spreads within a batch are observed to be much lower than the corresponding data sheet ones.The same can be said even with those among different batches. Fig. 9 shows the spread of V_GS(th) for the BUK7S1R5-40H for 10 different batches. In this case the 6-sigma spread is observed to be 0.42 V, from 2.86 V to 3.28 V. This value is calculated taking into account a small quantity of outliers (not shown in the plot of Fig. 9). Therefore, the observed worst case is given by a ΔV_GS(th) = 0.42 V or ΔV_GS(th),rel = ± 7 %, less than half of the guaranteed (data sheet) one.

Figure 9. V_GS(th) batches spread for BUK7S1R5-40H

Simulation 5 - Paralleled MOSFETs: V_GS(th) (data sheet vs. batch) spread

Simulation 5. Paralleled MOSFETs: V_GS(th) (data sheet vs batch) Spread.

Circuit optimisation

There are different types of circuit modifications, each has a different impact on the current sharing. In the following section only one will be discussed, due to its most advantageous aspects.

Localized gate resistor

This type of circuit modification is the most advantageous, it has no major drawbacks and it is the simplest to implement. The modification involves splitting the gate resistor between a localized one close to the gate of each MOSFET and a common resistor at the driver side, as shown in Fig. 11 b. Doing so will counteract the spreads and improve the sharing, mainly during switching with little impact during conduction. It is important to keep the localized resistance as low as possible to give maximum coupling between the MOSFET gates, effectively allowing the input capacitances to be considered in parallel. A simple simulation can display this effect: two circuits modelling the driver and input impedance of each MOSFET are used as comparison. Fig. 11 a. shows the control voltage at each MOSFET gate, the voltage is slowed down in case of the MOSFET with higher C_iss, vice versa it is less filtered in case of lower capacitance. By splitting the gate resistor the difference between the control voltages at each gate becomes negligible (Fig. 11 b).

Figure 11. SPICE simulation circuit: gate resistor split comparison

With reference to the naming adopted in the SPICE circuits of Fig. 11, the gate resistor at the driver can be calculated as:

(Eq. 5)  

The value of R_G,drv has been rounded to 12 Ω. A smaller R_G,drv can be beneficial by reducing the switching time where the unequal sharing occurs. In a similar manner, the smaller R_G,split the better coupled the MOSFETs gate, but it is recommended not to go below 2-3 Ω. In general, a gate resistor helps in dampening any oscillation in the gate-source loop that might compromise the EMC performance of the system. Therefore, given a lower resistance of the gate resistor, it is important to reduce as much as possible the loop inductance of the driver loop.

The great improvement of the resistor split can be easily appreciated by simulating the same half-bridge circuit using two different gate resistors setups and introducing some spread. This time an arbitrary combination of all the spreads has been used.

Figure 12. Gate-source voltage without and with gate resistor split

Simulation 6?- Paralleled MOSFETs: gate resistor split

Simulation 6. Paralleled MOSFETs: Gate Resistor Split

The simulations setup and results are summarized in Table 5 and Table 6, while a final comparison is given in Table 7. M3 is dissipating 8.2 W, M2 1.3 W and M1 2.0 W. At turn-ON M1 is switching first, due to having both lower Q_G(tot) and V_GS(th), thus handling the majority of the current. On the other hand, at turn-OFF the MOSFET with higher input charge (M3) will switch last and carry most of the current.

With the gate resistor split M3 is now dissipating 3.8 W, M2 2.0 W and M1 1.6 W. The improvements are noticeable both at turn-ON, where the peaks are now almost identical, and turn-OFF. Sharing during conduction has improved as well, this is due to time it takes for the current to reach its conduction value following the turn-ON event. Overall, M3 is now dissipating 50 % less power.

PCB layout influence

Tight spreads and a good layout are two important factors when designing an application with paralleled MOSFETs. This section describes guidelines to achieve a good layout and how parasitics influence the current sharing.

In a paralleled set of MOSFETs it is impossible to say beforehand where the device with lowest or highest spreads will be placed. Therefore, it is important to lay out each branch in the same way, failing to do so will result in the worsening of the worst case scenario.

Layout-dependent parasitics

In case of paralleled devices loop inductance and resistance in the path should be not only minimised but also equalised for each branch.

Higher inductance slows down the current reaching its steady state value due to the higher time constant of the circuit (τ = L/R), as shown in Fig. 13. The inductance decreases the peak current slightly but increases the overall sharing unbalance.

Figure 13. MOSFETs drain current (I_D) - effects of parasitic inductance

Figure 15. MOSFETs drain current (I_D) - effects of parasitic inductance imbalance

Circuit PCB layout

Electronic system, almost as much as the quality of the parts. In case of paralleled MOSFETs the layout should be designed to provide: good thermal link between the devices, low and equal loop inductance in the gate-source and source-drain loops and low and equal resistance between the branches.

Good thermal coupling allows the devices to operate at similar lower temperatures. Furthermore, the designer should aim at obtaining similar Rth(mb-amb)for each MOSFET. Multiple planes and thermal vias help in improving the heat exchange between devices and environment. Care should be taken in the placement of the MOSFETs: for instance by avoiding placing a subset of the MOSFETs near heat sinks, connectors or other components that may be keep them cooler than the other paralleled MOSFETs. For more information about this topic refer to AN90003: LFPAK MOSFET thermal design guide.

The results of the current density simulation for the low side and high side are shown in Fig. 19. Higher current density is shown in red, while low or null in blue. For instancethe high side simulation highlights a spot around M4 and inlet VBUS1 where current density is higher, due to the position of the latter. By integrating the current density over the entire surface of the die it is possible to calculate the sharing in steady state of the layout (between 30-40% in this particular case). These simulations have been obtained using scSTREAM.

Figure 19. CFD current density simulation: Low side MOSFETs ON – Top side,  Low side MOSFETs ON – Bottom side,  High side MOSFETs ON – Top side

Driving paralleled MOSFETs

When driving paralleled MOSFETs it is recommended to use one single gate driver. This is mainly done to synchronize the devices operation as much as possible.

The gate driver should have enough peak current capability to fully charge and discharge the total input capacitance of the paralleled MOSFETs. This requirement becomes more and more stringent as the number of MOSFETs increases, especially if the switching time is required to be low, as the total input capacitance is now C_iss,= n.FETs × C_iss,max. Failing to do so means that the switching tot speed will be set by the gate driver itself and not by the gate resistor.