74CBTLV3126
4-bit bus switch
The 74CBTLV3126 provides a 4-bit high-speed bus switch with separate output enable inputs (1OE to 4OE). The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The switch is disabled (high-impedance OFF-state) when the output enable (nOE) input is LOW.
To ensure the high-impedance OFF-state during power-up or power-down, nOE should be tied to the GND through a pull-down resistor. The minimum value of the resistor is determined by the current-sinking capability of the driver.
Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 2.3 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
Features and benefits
Supply voltage range from 2.3 V to 3.6 V
Standard '126'-type pinout
High noise immunity
Complies with JEDEC standard:
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
5 ? switch connection between two ports
Rail to rail switching on data I/O ports
CMOS low power consumption
Latch-up performance exceeds 250 mA per JESD78B Class I level A
IOFF circuitry provides partial Power-down mode operation
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
參數(shù)類型
| 型號(hào) | VCC (V) | VPASS (V) | Logic switching levels | RON (Ω) | f(-3dB) (MHz) | Nr of bits | tpd (ns) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74CBTLV3126BQ | 2.3?-?3.6 | 3.3 | CMOS/LVTTL | 7 | 400 | 4 | 0.2 | very low | -40~125 | 107 | 21.3 | 75 | DHVQFN14 |
| 74CBTLV3126DS | 2.3?-?3.6 | 3.3 | CMOS/LVTTL | 7 | 400 | 4 | 0.2 | very low | -40~125 | 148 | 42 | SSOP16 | |
| 74CBTLV3126PW | 2.3?-?3.6 | 3.3 | CMOS/LVTTL | 7 | 400 | 4 | 0.2 | very low | -40~125 | 141 | 8 | 68 | TSSOP14 |
封裝
| 型號(hào) | 可訂購(gòu)的器件編號(hào)，（訂購(gòu)碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74CBTLV3126BQ | 74CBTLV3126BQ,115 (935289342115) |
Active | V3126 |
DHVQFN14 (SOT762-1) |
SOT762-1 | SOT762-1_115 | |
| 74CBTLV3126DS | 74CBTLV3126DS,118 (935289343118) |
Active | TLV3126 |
SSOP16 (SOT519-1) |
SOT519-1 |
SSOP-TSSOP-VSO-REFLOW
SSOP-TSSOP-VSO-WAVE |
SOT519-1_118 |
| 74CBTLV3126PW | 74CBTLV3126PW,118 (935289344118) |
Active | TLV3126 |
TSSOP14 (SOT402-1) |
SOT402-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT402-1_118 |
環(huán)境信息
| 型號(hào) | 可訂購(gòu)的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74CBTLV3126BQ | 74CBTLV3126BQ,115 | 74CBTLV3126BQ |
|
|
| 74CBTLV3126DS | 74CBTLV3126DS,118 | 74CBTLV3126DS |
|
|
| 74CBTLV3126PW | 74CBTLV3126PW,118 | 74CBTLV3126PW |
|
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文檔 (14)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74CBTLV3126 | 4-bit bus switch | Data sheet | 2024-04-11 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| SOT762-1 | 3D model for products with SOT762-1 package | Design support | 2019-10-03 |
| SOT519-1 | 3D model for products with SOT519-1 package | Design support | 2023-02-07 |
| SOT402-1 | 3D model for products with SOT402-1 package | Design support | 2023-02-02 |
| cbtlv3126 | 74CBTLV3126 IBIS model | IBIS model | 2015-02-23 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| DHVQFN14_SOT762-1_mk | plastic, dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; 0.5 mm pitch; 2.5 mm x 3 mm x 0.85 mm body | Marcom graphics | 2017-01-28 |
| TSSOP14_SOT402-1_mk | plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.1 mm body | Marcom graphics | 2017-01-28 |
| SOT762-1 | plastic, leadless dual in-line compatible thermal enhanced very thin quad flat package; 14 terminals; 0.5 mm pitch; 2.5 x 3 x 1 mm body | Package information | 2023-04-05 |
| SOT519-1 | plastic, shrink small outline package; 16 leads; 0.635 mm pitch; 4.9 mm x 3.9 mm x 1.73 mm body | Package information | 2022-06-20 |
| SOT402-1 | plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.2 mm body | Package information | 2023-11-07 |
| SSOP-TSSOP-VSO-REFLOW | Footprint for reflow soldering | Reflow soldering | 2009-10-08 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
支持
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模型
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| SOT762-1 | 3D model for products with SOT762-1 package | Design support | 2019-10-03 |
| SOT519-1 | 3D model for products with SOT519-1 package | Design support | 2023-02-07 |
| SOT402-1 | 3D model for products with SOT402-1 package | Design support | 2023-02-02 |
| cbtlv3126 | 74CBTLV3126 IBIS model | IBIS model | 2015-02-23 |
Ordering, pricing & availability
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