74LVC2G67
Bilateral switch
The 74LVC2G67 is a dual single pole, single-throw analog switch. Each switch has two input/output terminals (nY and nZ) and a digital enable input (nE). When nE is HIGH, the analog switch is turned off. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
Very low ON resistance:
7.5 ? (typical) at VCC = 2.7 V
6.5 ? (typical) at VCC = 3.3 V
6 ? (typical) at VCC = 5 V
Switch current capability of 32 mA
Overvoltage tolerant inputs to 5.5 V
High noise immunity
CMOS low power consumption
TTL interface compatibility at 3.3 V
Latch-up performance meets requirements of JESD78 Class I
Complies with JEDEC standards:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
參數(shù)類型
| 型號 | Package name | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC2G67DC | VSSOP8 | |||||||||||||
| 74LVC2G67DP | SPST-NO | 1.65?-?5.5 | CMOS/LVTTL | 15 | 1.5 | 440 | 0.005 | - | very low | -40~125 | 196 | 15.1 | 99 | TSSOP8 |
| 74LVC2G67GT | XSON8 |
封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC2G67DC | 74LVC2G67DCH (935692625125) |
Active | V67 |
VSSOP8 (SOT765-1) |
SOT765-1 | SOT765-1_125 | |
| 74LVC2G67DP | 74LVC2G67DPH (935692627125) |
Active | V67 |
TSSOP8 (SOT505-2) |
SOT505-2 | SOT505-2_125 | |
| 74LVC2G67GT | 74LVC2G67GTX (935692629115) |
Development | V67 |
XSON8 (SOT833-1) |
SOT833-1 | SOT833-1_115 |
環(huán)境信息
| 型號 | 可訂購的器件編號 | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVC2G67DC | 74LVC2G67DCH | 74LVC2G67DC |
|
|
| 74LVC2G67DP | 74LVC2G67DPH | 74LVC2G67DP |
|
|
| 74LVC2G67GT | 74LVC2G67GTX | 74LVC2G67GT |
|
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文檔 (13)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74LVC2G67 | Bilateral switch | Data sheet | 2025-09-25 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| Nexperia_document_guide_MiniLogic_MicroPak_201808 | MicroPak leadless logic portfolio guide | Brochure | 2018-09-03 |
| SOT765-1 | 3D model for products with SOT765-1 package | Design support | 2020-01-22 |
| SOT505-2 | 3D model for products with SOT505-2 package | Design support | 2019-01-18 |
| SOT833-1 | 3D model for products with SOT833-1 package | Design support | 2021-01-28 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| VSSOP8_SOT765-1_mk | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Marcom graphics | 2017-01-28 |
| SOT765-1 | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Package information | 2022-06-03 |
| SOT505-2 | plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm body | Package information | 2022-06-03 |
| SOT833-1 | plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm body | Package information | 2022-06-03 |
| MAR_SOT833 | MAR_SOT833 Topmark | Top marking | 2013-06-03 |
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