74LVC1G18
1-of-2 non-inverting demultiplexer with 3-state deselected output
The 74LVC1G18 is a 1-to-2 demultiplexer with 3-state outputs. The device buffers the data on input A and passes it to output 1Y or 2Y, depending on whether the state of the select input (S) is LOW or HIGH. The unused output assumes the high impedence OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
Overvoltage tolerant inputs to 5.5 V
High noise immunity
±24 mA output drive (VCC = 3.0 V)
CMOS low power dissipation
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
IOFF circuitry provides partial Power-down mode operation
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 to +85 °C and -40 to +125 °C.
參數(shù)類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC1G18GV | 1.65?-?5.5 | CMOS/LVTTL | ± 32 | 2.3 | low | -40~125 | 231 | 39.1 | 145 | TSOP6 |
| 74LVC1G18GW | 1.65?-?5.5 | CMOS/LVTTL | ± 32 | 2.3 | low | -40~125 | 264 | 38.4 | 153 | TSSOP6 |
封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC1G18GV | 74LVC1G18GV,125 (935273782125) |
Active | V18 |
TSOP6 (SOT457) |
SOT457 |
WAVE_BG-BD-1
|
SOT457_125 |
| 74LVC1G18GW | 74LVC1G18GW,125 (935273781125) |
Active | VW |
TSSOP6 (SOT363-2) |
SOT363-2 | SOT363-2_125 |
環(huán)境信息
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVC1G18GV | 74LVC1G18GV,125 | 74LVC1G18GV |
|
|
| 74LVC1G18GW | 74LVC1G18GW,125 | 74LVC1G18GW |
|
|
文檔 (15)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74LVC1G18 | 1-of-2 non-inverting demultiplexer with 3-state deselected output | Data sheet | 2023-08-16 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| mnb088 | Block diagram: 74AUP1G18GF, 74AUP1G18GM, 74AUP1G18GW, 74LVC1G18GV, 74LVC1G18GW | Block diagram | 2009-11-03 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| SOT457 | 3D model for products with SOT457 package | Design support | 2022-11-04 |
| SOT363-2 | 3D model for products with SOT363-2 package | Design support | 2023-02-02 |
| lvc1g18 | 74LVC1G18 IBIS model | IBIS model | 2014-10-20 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| TSOP6_SOT457_mk | plastic, surface-mounted package (TSOP6); 6 leads; 0.95 mm pitch; 2.9 mm x 1.5 mm x 1 mm body | Marcom graphics | 2017-01-28 |
| SOT457 | plastic, surface-mounted package (SC-74; TSOP6); 6 leads | Package information | 2023-03-03 |
| SOT363-2 | plastic thin shrink small outline package; 6 leads; body width 1.25 mm | Package information | 2022-11-21 |
| MAR_SOT457 | MAR_SOT457 Topmark | Top marking | 2013-06-03 |
| WAVE_BG-BD-1 | Wave soldering profile | Wave soldering | 2021-09-08 |
支持
如果您需要設計/技術(shù)支持，請告知我們并填寫 應答表 我們會盡快回復您。
Ordering, pricing & availability
樣品
作為 Nexperia 的客戶，您可以通過我們的銷售機構(gòu)訂購樣品。
如果您沒有 Nexperia 的直接賬戶，我們的全球和地區(qū)分銷商網(wǎng)絡可為您提供 Nexperia 樣品支持。查看官方經(jīng)銷商列表。