NXU0102-Q100
2-bit dual-supply buffer/level translator with Schmitt-trigger; 3-state
The NXU0102-Q100 is a 2-bit, dual-supply level translating buffer with Schmitt-trigger inputs and 3-state outputs. It features two data inputs (A1 and A2), two data outputs (YB1 and YB2), and an output enable input (OE).
Both VCCA and VCCB can be supplied at any voltage between 0.9 V and 5.5 V making the device suitable for translating between any of the voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V).
This device facilitates asynchronous communication between data buses. Transmit data with a fixed direction (unidirectionally) from the A bus to the B bus on two channels. The OE pin can be referenced to VCCA and VCCB domain and when OE pin is set LOW the outputs are disabled and enter a high-impedance OFF-state which isolates the buses. The OE pin can be left floating or externally pulled down to ground to ensure the high-impedance state of the outputs during power up or power down.
This device ensures low static and dynamic power consumption across the entire supply range and is fully specified for partial power down applications using IOFF. The IOFF circuitry prevents potentially damaging backflow current through the device when it is powered down or if one of the power supplies is disconnected (floating).
No power supply sequencing is required and output glitches during power supply transitions are prevented. As a result, glitches will not appear on the outputs for supply transitions during power-up/down.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range:
VCCA: 0.9 V to 5.5 V
VCCB: 0.9 V to 5.5 V
- Low power consumption for supply voltage range 1.1 V to 5.5 V
- 3 μA (Tamb = 25 °C)
- 5 μA (Tamb = -40 °C to +125 °C)
- Schmitt-trigger inputs with integrated static high ohmic pull-down resistor on the input
Maximum data rates:
250 Mbps (≥ 1.8 V to 5 V translation)
High output drive 12 mA at 5 V
Output enable (OE) allows connection to VCCA or VCCB domain
Suspend mode when either one of the supply voltages is below 100 mV or disconnected (floating)
Low noise overshoot and undershoot <10% of VCCO
IOFF circuitry provides partial power-down mode operation
Latch-up performance exceeds 100 mA per JESD78D Class II
Complies with JEDEC standard:
JESD8-12 (0.9 V to 1.3 V)
JESD8-11 (1.4 V to 1.6 V)
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD12-6 (4.5 V to 5.5 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2500 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1500 V
- Similar function: NXU0202-Q100
Applications
- General purpose I/O level translation
- Noisy environments or slow input signals
- Supports push-pull voltage translation as 2-wire UART and 2-pin JTAG protocols
- Consumer
參數(shù)類(lèi)型
| 型號(hào) | Logic switching levels | Output drive capability (mA) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|
| NXU0102DC-Q100 | CMOS/LVTTL | ± 12 | 4 | ultra low | -40~125 | 189 | 98 | 25 | VSSOP8 |
| NXU0102GT-Q100 | CMOS/LVTTL | ± 12 | 4 | ultra low | -40~125 | 276 | 121 | 3.3 | XSON8 |
封裝
| 型號(hào) | 可訂購(gòu)的器件編號(hào)，（訂購(gòu)碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| NXU0102DC-Q100 | NXU0102DC‑Q100H (935691946125) |
Active | L2 |
VSSOP8 (SOT765-1) |
SOT765-1 | SOT765-1_125 | |
| NXU0102GT-Q100 | NXU0102GT‑Q100X (935691949115) |
Active | L2 |
XSON8 (SOT833-1) |
SOT833-1 | SOT833-1_115 |
環(huán)境信息
| 型號(hào) | 可訂購(gòu)的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| NXU0102DC-Q100 | NXU0102DC‑Q100H | NXU0102DC-Q100 |
|
|
| NXU0102GT-Q100 | NXU0102GT‑Q100X | NXU0102GT-Q100 |
|
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文檔 (13)
| 文件名稱(chēng) | 標(biāo)題 | 類(lèi)型 | 日期 |
|---|---|---|---|
| NXU0102_Q100 | 2-bit dual-supply buffer/level translator with Schmitt-trigger; 3-state | Data sheet | 2025-01-30 |
| AN90057 | Pin FMEA for NXU family | Application note | 2024-09-11 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| Nexperia_document_guide_MiniLogic_MicroPak_201808 | MicroPak leadless logic portfolio guide | Brochure | 2018-09-03 |
| SOT765-1 | 3D model for products with SOT765-1 package | Design support | 2020-01-22 |
| SOT833-1 | 3D model for products with SOT833-1 package | Design support | 2021-01-28 |
| nxu0102 | NXU0102 IBIS model | IBIS model | 2024-10-31 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| VSSOP8_SOT765-1_mk | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Marcom graphics | 2017-01-28 |
| SOT765-1 | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Package information | 2022-06-03 |
| SOT833-1 | plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm body | Package information | 2022-06-03 |
| MAR_SOT833 | MAR_SOT833 Topmark | Top marking | 2013-06-03 |
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