74LVC2G34-Q100
Dual buffer gate
The 74LVC2G34-Q100 is a dual buffer. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and -40 °C to +125 °C
Wide supply voltage range from 1.65 V to 5.5 V
Overvoltage tolerant inputs to 5.5 V
High noise immunity
±24 mA output drive (VCC = 3.0 V)
CMOS low power dissipation
IOFF provides partial Power-down mode operation
Direct interface with TTL levels
Latch-up performance exceeds 250 mA
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
參數(shù)類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC2G34GM-Q100 | 1.65?-?5.5 | CMOS/LVTTL | ± 32 | 175 | 2 | low | -40~125 | 290 | 6.5 | 145 | XSON6 |
| 74LVC2G34GV-Q100 | 1.65?-?5.5 | CMOS/LVTTL | ± 32 | 175 | 2 | low | -40~125 | 231 | 39.1 | 145 | TSOP6 |
| 74LVC2G34GW-Q100 | 1.65?-?5.5 | CMOS/LVTTL | ± 32 | 175 | 2 | low | -40~125 | 264 | 38.4 | 153 | TSSOP6 |
封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC2G34GM-Q100 | 74LVC2G34GM‑Q100,1 (935299049125) |
Active | YA |
XSON6 (SOT886) |
SOT886 | SOT886_125 | |
| 74LVC2G34GV-Q100 | 74LVC2G34GV‑Q100,1 (935299051125) |
Active | Y34 |
TSOP6 (SOT457) |
SOT457 |
WAVE_BG-BD-1
|
SOT457_125 |
| 74LVC2G34GW-Q100 | 74LVC2G34GW‑Q100,1 (935299052125) |
Active | YA |
TSSOP6 (SOT363-2) |
SOT363-2 | SOT363-2_125 |
環(huán)境信息
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVC2G34GM-Q100 | 74LVC2G34GM‑Q100,1 | 74LVC2G34GM-Q100 |
|
|
| 74LVC2G34GV-Q100 | 74LVC2G34GV‑Q100,1 | 74LVC2G34GV-Q100 |
|
|
| 74LVC2G34GW-Q100 | 74LVC2G34GW‑Q100,1 | 74LVC2G34GW-Q100 |
|
|
文檔 (23)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74LVC2G34_Q100 | Dual buffer gate | Data sheet | 2023-08-22 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| mnb063 | Block diagram: 74HC2G34GV, 74HC2G34GW, 74HCT2G34GV, 74HCT2G34GW, 74LVC2G34GF, 74LVC2G34GM, 74LVC2G34GV, 74LVC2G34GW, 74AUP2G34GF, 74AUP2G34GM, 74AUP2G34GW | Block diagram | 2009-11-03 |
| Nexperia_document_guide_MiniLogic_MicroPak_201808 | MicroPak leadless logic portfolio guide | Brochure | 2018-09-03 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| SOT886 | 3D model for products with SOT886 package | Design support | 2019-10-03 |
| SOT457 | 3D model for products with SOT457 package | Design support | 2022-11-04 |
| SOT363-2 | 3D model for products with SOT363-2 package | Design support | 2023-02-02 |
| lvc2g34 | 74LVC2G34 IBIS model | IBIS model | 2015-09-06 |
| Nexperia_document_leaflet_Logic_Automotive_MicroPak_solutions_201904 | Automotive logic in MicroPak leadless packages | Leaflet | 2019-04-18 |
| Nexperia_document_leaflet_Logic_X2SON_packages_062018 | X2SON ultra-small 4, 5, 6 & 8-pin leadless packages | Leaflet | 2018-06-05 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| DFN1410-6_SOT886_mk | plastic, extremely thin small outline package; no leads; 6 terminals; 0.6 mm pitch; 1 mm x 1.45 mm x 0.5 mm body | Marcom graphics | 2017-01-28 |
| XSON6_SOT886_mk | plastic, extremely thin small outline package; no leads; 6 terminals; 0.6 mm pitch; 1 mm x 1.45 mm x 0.5 mm body | Marcom graphics | 2017-01-28 |
| TSOP6_SOT457_mk | plastic, surface-mounted package (TSOP6); 6 leads; 0.95 mm pitch; 2.9 mm x 1.5 mm x 1 mm body | Marcom graphics | 2017-01-28 |
| SOT886 | plastic, leadless extremely thin small outline package; 6 terminals; 0.5 mm pitch; 1 mm x 1.45 mm x 0.5 mm body | Package information | 2022-06-01 |
| SOT457 | plastic, surface-mounted package (SC-74; TSOP6); 6 leads | Package information | 2023-03-03 |
| SOT363-2 | plastic thin shrink small outline package; 6 leads; body width 1.25 mm | Package information | 2022-11-21 |
| MAR_SOT886 | MAR_SOT886 Topmark | Top marking | 2013-06-03 |
| MAR_SOT457 | MAR_SOT457 Topmark | Top marking | 2013-06-03 |
| WAVE_BG-BD-1 | Wave soldering profile | Wave soldering | 2021-09-08 |
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