74LV74-Q100
Dual D-type flip-flop with set and reset; positive-edge trigger
The 74LV74-Q100 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the D?-?input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the nQ output. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 1.0 V to 5.5 V
Optimized for low voltage applications from 1.0 V to 3.6 V
CMOS low power dissipation
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Direct interface with TTL levels (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
參數(shù)類型
| 型號(hào) | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LV74D-Q100 | 1.0?-?5.5 | TTL | ± 12 | 11 | 75 | low | -40~125 | 83 | 3.7 | 41 | SO14 |
| 74LV74PW-Q100 | 1.0?-?5.5 | TTL | ± 12 | 11 | 75 | low | -40~125 | 124 | 2 | 47.9 | TSSOP14 |
封裝
| 型號(hào) | 可訂購的器件編號(hào)，（訂購碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LV74D-Q100 | 74LV74D‑Q100J (935301551118) |
Active | 74LV74D |
SO14 (SOT108-1) |
SOT108-1 |
SO-SOJ-REFLOW
SO-SOJ-WAVE WAVE_BG-BD-1 |
SOT108-1_118 |
| 74LV74PW-Q100 | 74LV74PW‑Q100J (935301552118) |
Active | LV74 |
TSSOP14 (SOT402-1) |
SOT402-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT402-1_118 |
環(huán)境信息
| 型號(hào) | 可訂購的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LV74D-Q100 | 74LV74D‑Q100J | 74LV74D-Q100 |
|
|
| 74LV74PW-Q100 | 74LV74PW‑Q100J | 74LV74PW-Q100 |
|
|
文檔 (15)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74LV74_Q100 | Dual D-type flip-flop with set and reset; positive-edge trigger | Data sheet | 2024-04-08 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| SOT108-1 | 3D model for products with SOT108-1 package | Design support | 2020-01-22 |
| SOT402-1 | 3D model for products with SOT402-1 package | Design support | 2023-02-02 |
| lv74 | 74LV74 IBIS model | IBIS model | 2019-01-09 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| SO14_SOT108-1_mk | plastic, small outline package; 14 leads; 1.27 mm pitch; 8.65 mm x 3.9 mm x 1.75 mm body | Marcom graphics | 2017-01-28 |
| TSSOP14_SOT402-1_mk | plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.1 mm body | Marcom graphics | 2017-01-28 |
| SOT108-1 | plastic, small outline package; 14 leads; 1.27 mm pitch; 8.65 mm x 3.9 mm x 1.75 mm body | Package information | 2023-11-07 |
| SOT402-1 | plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.2 mm body | Package information | 2023-11-07 |
| SO-SOJ-REFLOW | Footprint for reflow soldering | Reflow soldering | 2009-10-08 |
| lv | lv Spice model | SPICE model | 2013-05-07 |
| SO-SOJ-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
| WAVE_BG-BD-1 | Wave soldering profile | Wave soldering | 2021-09-08 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
支持
如果您需要設(shè)計(jì)/技術(shù)支持，請(qǐng)告知我們并填寫 應(yīng)答表 我們會(huì)盡快回復(fù)您。
Ordering, pricing & availability
樣品
作為 Nexperia 的客戶，您可以通過我們的銷售機(jī)構(gòu)訂購樣品。
如果您沒有 Nexperia 的直接賬戶，我們的全球和地區(qū)分銷商網(wǎng)絡(luò)可為您提供 Nexperia 樣品支持。查看官方經(jīng)銷商列表。