可訂購部件
| 型號 | 可訂購的器件編號 | 訂購代碼(12NC) | 封裝 | 從經(jīng)銷商處購買 |
|---|---|---|---|---|
| 74AHCT573D | 74AHCT573D,118 | 935263073118 | SOT163-1 | 訂單產(chǎn)品 |
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Click here for more information74AHCT573D
Octal D-type transparent latch; 3-state
The 74AHC573; 74AHCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments.
Alternatives
Features and benefits
Wide supply voltage range from 2.0 V to 5.5 V
Balanced propagation delays
All inputs have Schmitt-trigger action
Overvoltage tolerant inputs to 5.5 V
High noise immunity
CMOS low power dissipation
Common 3-state output enable input
Functionally identical to the 74AHC373; 74AHCT373
Input levels:
For 74AHC573: CMOS input level
For 74AHCT573: TTL input level
- ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Latch-up performance exceeds 100 mA per JESD 78 Class II Level A
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
參數(shù)類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|
| 74AHCT573D | 4.5?-?5.5 | TTL | ± 8 | 3.9 | low | -40~125 | 84 | 26.4 | 60 | SO20 |
PCB Symbol, Footprint and 3D Model
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封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74AHCT573D | 74AHCT573D,118 (935263073118) |
Active | 74AHCT573D |
SO20 (SOT163-1) |
SOT163-1 |
WAVE_BG-BD-1
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SOT163-1_118 |
Series
文檔 (10)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74AHC_AHCT573 | Octal D-type transparent latch; 3-state | Data sheet | 2023-10-11 |
| AN11106 | Pin FMEA for AHC/AHCT family | Application note | 2019-01-09 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| SOT163-1 | 3D model for products with SOT163-1 package | Design support | 2020-01-22 |
| ahct573 | ahct573 IBIS model | IBIS model | 2013-04-08 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| SOT163-1 | plastic, small outline package; 20 leads; 1.27 mm pitch; 12.8 mm x 7.5 mm x 2.65 mm body | Package information | 2024-11-15 |
| SOT163-1_118 | SO20; Reel pack for SMD, 13"; Q1/T1 product orientation | Packing information | 2022-08-01 |
| 74AHCT573D_Nexperia_Product_Reliability | 74AHCT573D Nexperia Product Reliability | Quality document | 2025-03-20 |
| WAVE_BG-BD-1 | Wave soldering profile | Wave soldering | 2021-09-08 |
Longevity
The Nexperia Longevity Program is aimed to provide our customers information from time to time about the expected time that our products can be ordered. The NLP is reviewed and updated regularly by our Executive Management Team. View our longevity program here.
PCB Symbol, Footprint and 3D Model
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訂購、定價與供貨
| 型號 | Orderable part number | Ordering code (12NC) | 狀態(tài) | 包裝 | Packing Quantity | 在線購買 |
|---|---|---|---|---|---|---|
| 74AHCT573D | 74AHCT573D,118 | 935263073118 | Active | SOT163-1_118 | 2,000 |
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樣品
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.