可訂購部件
| 型號 | 可訂購的器件編號 | 訂購代碼(12NC) | 封裝 | 從經(jīng)銷商處購買 |
|---|---|---|---|---|
| 74AHCU04BQ-Q100 | 74AHCU04BQ-Q100X | 935300742115 | SOT762-1 | 訂單產(chǎn)品 |
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Click here for more information74AHCU04BQ-Q100
Hex unbuffered inverter
The 74AHCU04-Q100 is high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A.
The 74AHCU04-Q100 is a general-purpose hex unbuffered inverter. Each of the six inverters is a single stage.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Low power dissipation
Balanced propagation delays
Inputs accept voltages higher than VCC
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints
參數(shù)類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AHCU04BQ‑Q100 | 2.0?-?5.5 | CMOS | ± 8 | 60 | 6 | low | -40~125 | 106 | 20.9 | 74 | DHVQFN14 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74AHCU04BQ‑Q100 | 74AHCU04BQ‑Q100X (935300742115) |
Active | AHU04 |
DHVQFN14 (SOT762-1) |
SOT762-1 | SOT762-1_115 |
環(huán)境信息
| 型號 | 可訂購的器件編號 | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74AHCU04BQ‑Q100 | 74AHCU04BQ‑Q100X | 74AHCU04BQ-Q100 |
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Series
文檔 (9)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74AHCU04_Q100 | Hex unbuffered inverter | Data sheet | 2024-01-25 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| SOT762-1 | 3D model for products with SOT762-1 package | Design support | 2019-10-03 |
| ahcu04 | ahcu04 IBIS model | IBIS model | 2013-04-08 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| DHVQFN14_SOT762-1_mk | plastic, dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; 0.5 mm pitch; 2.5 mm x 3 mm x 0.85 mm body | Marcom graphics | 2017-01-28 |
| SOT762-1 | plastic, leadless dual in-line compatible thermal enhanced very thin quad flat package; 14 terminals; 0.5 mm pitch; 2.5 x 3 x 1 mm body | Package information | 2023-04-05 |
| SOT762-1_115 | DHVQFN14; Reel pack for SMD, 7"; Q1/T1 product orientation | Packing information | 2025-10-24 |
| 74AHCU04BQ-Q100_Nexperia_Product_Reliability | 74AHCU04BQ-Q100 Nexperia Product Reliability | Quality document | 2025-03-20 |
Longevity
The Nexperia Longevity Program is aimed to provide our customers information from time to time about the expected time that our products can be ordered. The NLP is reviewed and updated regularly by our Executive Management Team. View our longevity program here.
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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訂購、定價與供貨
| 型號 | Orderable part number | Ordering code (12NC) | 狀態(tài) | 包裝 | Packing Quantity | 在線購買 |
|---|---|---|---|---|---|---|
| 74AHCU04BQ‑Q100 | 74AHCU04BQ‑Q100X | 935300742115 | Active | SOT762-1_115 | 3,000 |
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樣品
作為 Nexperia 的客戶，您可以通過我們的銷售機構(gòu)訂購樣品。
如果您沒有 Nexperia 的直接賬戶，我們的全球和地區(qū)分銷商網(wǎng)絡(luò)可為您提供 Nexperia 樣品支持。查看官方經(jīng)銷商列表。
How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.