可訂購部件
| 型號 | 可訂購的器件編號 | 訂購代碼(12NC) | 封裝 | 從經(jīng)銷商處購買 |
|---|---|---|---|---|
| 74ALVC00PW | 74ALVC00PW,118 | 935269711118 | SOT402-1 | 訂單產(chǎn)品 |
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Click here for more information74ALVC00PW
Quad 2-input NAND gate
The 74ALVC00 is a quad 2-input NAND gate.
Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Alternatives
Features and benefits
Wide supply voltage range from 1.65 V to 3.6 V
CMOS low power dissipation
Overvoltage tolerant inputs to 3.6 V
Direct interface with TTL levels
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 250 mA per JESD78 Class II.A
Complies with JEDEC standards:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
參數(shù)類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74ALVC00PW | 1.65?-?3.6 | TTL | ± 24 | 2.1 | 145 | 4 | low | -40~85 | 138 | 6.9 | 64 | TSSOP14 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74ALVC00PW | 74ALVC00PW,118 (935269711118) |
Active | ALVC00 |
TSSOP14 (SOT402-1) |
SOT402-1 |
SSOP-TSSOP-VSO-WAVE
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SOT402-1_118 |
環(huán)境信息
| 型號 | 可訂購的器件編號 | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74ALVC00PW | 74ALVC00PW,118 | 74ALVC00PW |
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文檔 (10)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74ALVC00 | Quad 2-input NAND gate | Data sheet | 2024-01-11 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| SOT402-1 | 3D model for products with SOT402-1 package | Design support | 2023-02-02 |
| alvc00 | alvc00 IBIS model | IBIS model | 2013-04-08 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| TSSOP14_SOT402-1_mk | plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.1 mm body | Marcom graphics | 2017-01-28 |
| SOT402-1 | plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.2 mm body | Package information | 2023-11-07 |
| SOT402-1_118 | TSSOP14; Reel pack for SMD, 13"; Q1/T1 product orientation | Packing information | 2025-01-16 |
| 74ALVC00PW_Nexperia_Product_Reliability | 74ALVC00PW Nexperia Product Reliability | Quality document | 2025-03-20 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
Longevity
The Nexperia Longevity Program is aimed to provide our customers information from time to time about the expected time that our products can be ordered. The NLP is reviewed and updated regularly by our Executive Management Team. View our longevity program here.
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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訂購、定價(jià)與供貨
| 型號 | Orderable part number | Ordering code (12NC) | 狀態(tài) | 包裝 | Packing Quantity | 在線購買 |
|---|---|---|---|---|---|---|
| 74ALVC00PW | 74ALVC00PW,118 | 935269711118 | Active | SOT402-1_118 | 2,500 |
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樣品
作為 Nexperia 的客戶，您可以通過我們的銷售機(jī)構(gòu)訂購樣品。
如果您沒有 Nexperia 的直接賬戶，我們的全球和地區(qū)分銷商網(wǎng)絡(luò)可為您提供 Nexperia 樣品支持。查看官方經(jīng)銷商列表。
How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.