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Click here for more information74ALVCH16374DL
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
The 74ALVCH16374 is a 16-bit edge-triggered D-type flip-flop with bus hold inputs and 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. The device features two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 8-bits. The flip?-?flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high?-?impedance OFF-state. Operation of the nOE input does not affect the state of the flip?-?flops.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Alternatives
Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power dissipation
MULTIBYTE? flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold
Latch-up performance exceeds 100 mA per JESD 78 Class II.A
Output drive capability 50 Ω transmission lines at 85 °C
IOFF circuitry provides partial Power-down mode operation
Current drive ±24 mA at VCC = 3.0 V
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Complies with JEDEC standards:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C/JESD36 (2.7 V to 3.6 V)
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ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C
參數(shù)類型
| 型號 | Package name |
|---|---|
| 74ALVCH16374DL | SSOP48 |
封裝
下表中的所有產(chǎn)品型號均已停產(chǎn) 。
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74ALVCH16374DL | 74ALVCH16374DL,112 (935260444112) |
Obsolete | ALVCH16374 Standard Procedure Standard Procedure |
SSOP48 (SOT370-1) |
SOT370-1 |
SSOP-TSSOP-VSO-REFLOW
SSOP-TSSOP-VSO-WAVE |
暫無信息 |
| 74ALVCH16374DL,118 (935260444118) |
Obsolete | ALVCH16374 Standard Procedure Standard Procedure | SOT370-1_118 |
環(huán)境信息
下表中的所有產(chǎn)品型號均已停產(chǎn) 。
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74ALVCH16374DL | 74ALVCH16374DL,112 | 74ALVCH16374DL |
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| 74ALVCH16374DL | 74ALVCH16374DL,118 | 74ALVCH16374DL |
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Series
文檔 (7)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74ALVCH16374 | 2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state | Data sheet | 2024-06-19 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| alvch16374 | alvch16374 IBIS model | IBIS model | 2013-04-08 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| SOT370-1 | plastic, shrink small outline package; 48 leads; 0.635 mm pitch; 15.9 mm x 7.5 mm x 2.8 mm body | Package information | 2020-04-21 |
| SSOP-TSSOP-VSO-REFLOW | Footprint for reflow soldering | Reflow soldering | 2009-10-08 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
Longevity
The Nexperia Longevity Program is aimed to provide our customers information from time to time about the expected time that our products can be ordered. The NLP is reviewed and updated regularly by our Executive Management Team. View our longevity program here.
模型
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| alvch16374 | alvch16374 IBIS model | IBIS model | 2013-04-08 |
How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.