可訂購(gòu)部件
| 型號(hào) | 可訂購(gòu)的器件編號(hào) | 訂購(gòu)代碼(12NC) | 封裝 | 從經(jīng)銷(xiāo)商處購(gòu)買(mǎi) |
|---|---|---|---|---|
| 74AUP1G86GW-Q100 | 74AUP1G86GW-Q100H | 935305309125 | SOT353-1 | 訂單產(chǎn)品 |
Register once, drag and drop ECAD models into your CAD tool and speed up your design.
Click here for more information74AUP1G86GW-Q100
Low-power 2-input EXCLUSIVE-OR gate
The 74AUP1G86-Q100 is a single 2-input EXCLUSIVE-OR gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 0.8 V to 3.6 V
CMOS low power dissipation
High noise immunity
Low static power consumption; ICC = 0.9 μA (maximum)
Overvoltage tolerant inputs to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
參數(shù)類(lèi)型
| 型號(hào) | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP1G86GW‑Q100 | 0.8?-?3.6 | CMOS | ± 1.9 | 9 | 70 | 1 | ultra low | -40~125 | 309 | 79.2 | 179 | TSSOP5 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
|
|
封裝
| 型號(hào) | 可訂購(gòu)的器件編號(hào)，（訂購(gòu)碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74AUP1G86GW‑Q100 | 74AUP1G86GW‑Q100H (935305309125) |
Active | pH |
TSSOP5 (SOT353-1) |
SOT353-1 |
WAVE_BG-BD-1
|
SOT353-1_125 |
環(huán)境信息
| 型號(hào) | 可訂購(gòu)的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74AUP1G86GW‑Q100 | 74AUP1G86GW‑Q100H | 74AUP1G86GW-Q100 |
|
|
Series
文檔 (14)
| 文件名稱(chēng) | 標(biāo)題 | 類(lèi)型 | 日期 |
|---|---|---|---|
| 74AUP1G86_Q100 | Low-power 2-input EXCLUSIVE-OR gate | Data sheet | 2023-07-14 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN11052 | Pin FMEA for AUP family | Application note | 2019-01-09 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| SOT353-1 | 3D model for products with SOT353-1 package | Design support | 2019-09-23 |
| aup1g86 | 74AUP1G86 IBIS model | IBIS model | 2014-12-14 |
| Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Leaflet | 2019-04-12 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| TSSOP5_SOT353-1_mk | plastic, thin shrink small outline package; 5 leads; 0.65 mm pitch; 2 mm x 1.25 mm x 0.95 mm body | Marcom graphics | 2018-07-25 |
| SOT353-1 | plastic thin shrink small outline package; 5 leads; body width 1.25 mm | Package information | 2022-11-15 |
| SOT353-1_125 | TSSOP5; Reel pack for SMD, 7"; Q3/T4 product orientation | Packing information | 2023-02-21 |
| 74AUP1G86GW-Q100_Nexperia_Product_Reliability | 74AUP1G86GW-Q100 Nexperia Product Reliability | Quality document | 2025-03-20 |
| WAVE_BG-BD-1 | Wave soldering profile | Wave soldering | 2021-09-08 |
Longevity
The Nexperia Longevity Program is aimed to provide our customers information from time to time about the expected time that our products can be ordered. The NLP is reviewed and updated regularly by our Executive Management Team. View our longevity program here.
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
|
|
訂購(gòu)、定價(jià)與供貨
| 型號(hào) | Orderable part number | Ordering code (12NC) | 狀態(tài) | 包裝 | Packing Quantity | 在線(xiàn)購(gòu)買(mǎi) |
|---|---|---|---|---|---|---|
| 74AUP1G86GW‑Q100 | 74AUP1G86GW‑Q100H | 935305309125 | Active | SOT353-1_125 | 3,000 |
|
樣品
作為 Nexperia 的客戶(hù)，您可以通過(guò)我們的銷(xiāo)售機(jī)構(gòu)訂購(gòu)樣品。
如果您沒(méi)有 Nexperia 的直接賬戶(hù)，我們的全球和地區(qū)分銷(xiāo)商網(wǎng)絡(luò)可為您提供 Nexperia 樣品支持。查看官方經(jīng)銷(xiāo)商列表。
How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.