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Click here for more information74AXP1G32GN
Low-power 2-input OR gate
The 74AXP1G32 is a single 2-input OR gate.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device ensures very low static and dynamic power consumption across the entire VCC range from 0.7 V to 2.75 V. It is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features and benefits
Wide supply voltage range from 0.7 V to 2.75 V
Low input capacitance; CI = 0.5 pF (typical)
Low output capacitance; CO = 1.0 pF (typical)
Low dynamic power consumption; CPD = 2.4 pF at VCC = 1.2 V (typical)
Low static power consumption; ICC = 0.6 μA (85 °C maximum)
High noise immunity
Complies with JEDEC standard:
JESD8-12A.01 (1.1 V to 1.3 V)
JESD8-11A.01 (1.4 V to 1.6 V)
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A.01 (2.3 V to 2.7 V)
ESD protection:
HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
CDM JESD22-C101E exceeds 1000 V
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 2.75 V
Low noise overshoot and undershoot < 10% of VCC
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from -40 °C to +85 °C
參數類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AXP1G32GN | 0.7?-?2.75 | CMOS | ± 4.5 | 2.5 | 70 | 1 | ultra low | -40~85 | 366 | 28.6 | 226 |
封裝
下表中的所有產品型號均已停產 。
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74AXP1G32GN | 74AXP1G32GNH (935304046125) |
Obsolete | no package information | ||||
環(huán)境信息
下表中的所有產品型號均已停產 。
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74AXP1G32GN | 74AXP1G32GNH | 74AXP1G32GN |
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文檔 (4)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74AXP1G32 | Low-power 2-input OR gate | Data sheet | 2021-10-07 |
| axp1g32 | 74AXP1G32 IBIS model | IBIS model | 2014-10-22 |
| Nexperia_document_leaflet_Logic_AXP_technology_portfolio_201904 | AXP – Extremely low-power logic technology portfolio | Leaflet | 2019-04-05 |
| 74AXP1G32GN_Nexperia_Product_Reliability | 74AXP1G32GN Nexperia Product Reliability | Quality document | 2025-03-20 |
Longevity
The Nexperia Longevity Program is aimed to provide our customers information from time to time about the expected time that our products can be ordered. The NLP is reviewed and updated regularly by our Executive Management Team. View our longevity program here.
模型
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| axp1g32 | 74AXP1G32 IBIS model | IBIS model | 2014-10-22 |
How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.