74LVC1G386
3-input EXCLUSIVE-OR gate
The 74LVC1G386 is a single 3?-?input EXCLUSIVE?-?OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt?-?trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
Overvoltage tolerant inputs to 5.5 V
High noise immunity
CMOS low power dissipation
Direct interface with TTL levels
±24 mA output drive (VCC = 3.0 V)
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 250 mA
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 to +85 °C and -40 to +125 °C.
參數(shù)類型
| 型號(hào) | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC1G386GV | 1.65?-?5.5 | CMOS/LVTTL | ± 32 | 4.5 | 150 | 1 | low | -40~125 | 261 | 63.4 | 172 | TSOP6 |
| 74LVC1G386GW | 1.65?-?5.5 | CMOS/LVTTL | ± 32 | 4.5 | 150 | 1 | low | -40~125 | 284 | 56.7 | 172 | TSSOP6 |
封裝
| 型號(hào) | 可訂購(gòu)的器件編號(hào)，（訂購(gòu)碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC1G386GV | 74LVC1G386GV,125 (935274998125) |
Active | YH |
TSOP6 (SOT457) |
SOT457 |
WAVE_BG-BD-1
|
SOT457_125 |
| 74LVC1G386GW | 74LVC1G386GW,125 (935274997125) |
Active | YH |
TSSOP6 (SOT363-2) |
SOT363-2 | SOT363-2_125 |
環(huán)境信息
| 型號(hào) | 可訂購(gòu)的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVC1G386GV | 74LVC1G386GV,125 | 74LVC1G386GV |
|
|
| 74LVC1G386GW | 74LVC1G386GW,125 | 74LVC1G386GW |
|
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文檔 (15)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74LVC1G386 | 3-input EXCLUSIVE-OR gate | Data sheet | 2023-08-25 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| mnb143 | Block diagram: 74AUP1G386GF, 74AUP1G386GM, 74AUP1G386GW, 74LVC1G386GV, 74LVC1G386GW | Block diagram | 2009-11-03 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| SOT457 | 3D model for products with SOT457 package | Design support | 2022-11-04 |
| SOT363-2 | 3D model for products with SOT363-2 package | Design support | 2023-02-02 |
| lvc1g386 | 74LVC1G386 IBIS model | IBIS model | 2016-06-29 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| TSOP6_SOT457_mk | plastic, surface-mounted package (TSOP6); 6 leads; 0.95 mm pitch; 2.9 mm x 1.5 mm x 1 mm body | Marcom graphics | 2017-01-28 |
| SOT457 | plastic, surface-mounted package (SC-74; TSOP6); 6 leads | Package information | 2023-03-03 |
| SOT363-2 | plastic thin shrink small outline package; 6 leads; body width 1.25 mm | Package information | 2022-11-21 |
| MAR_SOT457 | MAR_SOT457 Topmark | Top marking | 2013-06-03 |
| WAVE_BG-BD-1 | Wave soldering profile | Wave soldering | 2021-09-08 |
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