74LVC00A-Q100
Quad 2-input NAND gate
The 74LVC00A-Q100 is a quad 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Overvoltage tolerant inputs to 5.5 V
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints
參數(shù)類型
| 型號(hào) | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC00ABQ-Q100 | 1.2?-?3.6 | CMOS/LVTTL | ± 24 | 2.1 | 150 | 4 | low | -40~125 | 109 | 23.4 | 77 | DHVQFN14 |
| 74LVC00AD-Q100 | 1.2?-?3.6 | CMOS/LVTTL | ± 24 | 2.1 | 150 | 4 | low | -40~125 | 112 | 22.6 | 70 | SO14 |
| 74LVC00APW-Q100 | 1.2?-?3.6 | CMOS/LVTTL | ± 24 | 2.1 | 150 | 4 | low | -40~125 | 144 | 8.7 | 70 | TSSOP14 |
封裝
| 型號(hào) | 可訂購(gòu)的器件編號(hào)，（訂購(gòu)碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC00ABQ-Q100 | 74LVC00ABQ‑Q100X (935300352115) |
Active | VC00A |
DHVQFN14 (SOT762-1) |
SOT762-1 | SOT762-1_115 | |
| 74LVC00AD-Q100 | 74LVC00AD‑Q100J (935300353118) |
Active | 74LVC00AD |
SO14 (SOT108-1) |
SOT108-1 |
SO-SOJ-REFLOW
SO-SOJ-WAVE WAVE_BG-BD-1 |
SOT108-1_118 |
| 74LVC00APW-Q100 | 74LVC00APW‑Q100J (935300354118) |
Active | LVC00A |
TSSOP14 (SOT402-1) |
SOT402-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT402-1_118 |
環(huán)境信息
| 型號(hào) | 可訂購(gòu)的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVC00ABQ-Q100 | 74LVC00ABQ‑Q100X | 74LVC00ABQ-Q100 |
|
|
| 74LVC00AD-Q100 | 74LVC00AD‑Q100J | 74LVC00AD-Q100 |
|
|
| 74LVC00APW-Q100 | 74LVC00APW‑Q100J | 74LVC00APW-Q100 |
|
|
文檔 (20)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74LVC00A_Q100 | Quad 2-input NAND gate | Data sheet | 2024-02-08 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| AN263 | Power considerations when using CMOS and BiCMOS logic devices | Application note | 2023-02-07 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| mna212 | Block diagram: 74LVC132ABQ, 74LVC132AD, 74LVC132APW, 74AHC00BQ, 74AHC00D, 74AHC00PW, 74AHCT00BQ, 74AHCT00D, 74AHCT00PW, 74LV00BQ, 74LV00D, 74LV00DB, 74LV00N, 74LV00PW, 74LVC00ABQ, 74LVC00AD, 74LVC00ADB, 74LVC00APW | Block diagram | 2009-11-04 |
| SOT762-1 | 3D model for products with SOT762-1 package | Design support | 2019-10-03 |
| SOT108-1 | 3D model for products with SOT108-1 package | Design support | 2020-01-22 |
| SOT402-1 | 3D model for products with SOT402-1 package | Design support | 2023-02-02 |
| lvc00a | lvc00a IBIS model | IBIS model | 2013-04-08 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| DHVQFN14_SOT762-1_mk | plastic, dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; 0.5 mm pitch; 2.5 mm x 3 mm x 0.85 mm body | Marcom graphics | 2017-01-28 |
| SO14_SOT108-1_mk | plastic, small outline package; 14 leads; 1.27 mm pitch; 8.65 mm x 3.9 mm x 1.75 mm body | Marcom graphics | 2017-01-28 |
| TSSOP14_SOT402-1_mk | plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.1 mm body | Marcom graphics | 2017-01-28 |
| SOT762-1 | plastic, leadless dual in-line compatible thermal enhanced very thin quad flat package; 14 terminals; 0.5 mm pitch; 2.5 x 3 x 1 mm body | Package information | 2023-04-05 |
| SOT108-1 | plastic, small outline package; 14 leads; 1.27 mm pitch; 8.65 mm x 3.9 mm x 1.75 mm body | Package information | 2023-11-07 |
| SOT402-1 | plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.2 mm body | Package information | 2023-11-07 |
| SO-SOJ-REFLOW | Footprint for reflow soldering | Reflow soldering | 2009-10-08 |
| SO-SOJ-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
| WAVE_BG-BD-1 | Wave soldering profile | Wave soldering | 2021-09-08 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
支持
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模型
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| SOT762-1 | 3D model for products with SOT762-1 package | Design support | 2019-10-03 |
| SOT108-1 | 3D model for products with SOT108-1 package | Design support | 2020-01-22 |
| SOT402-1 | 3D model for products with SOT402-1 package | Design support | 2023-02-02 |
| lvc00a | lvc00a IBIS model | IBIS model | 2013-04-08 |
Ordering, pricing & availability
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