74AHC2G08; 74AHCT2G08
Dual 2-input AND gate
The 74AHC2G08; 74AHCT2G08 is a dual 2-input AND gate. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments.
Features and benefits
Symmetrical output impedance
Balanced propagation delays
Wide supply voltage range from 2.0 to 5.5 V
Overvoltage tolerant inputs to 5.5 V
Input levels:
For 74AHC2G08: CMOS level
For 74AHCT2G08: TTL level
High noise immunity
CMOS low power dissipation
Latch-up performance exceeds 100 mA per JESD 78 Class II Level A
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +80 °C and from -40 °C to +125 °C
參數(shù)類型
| 型號(hào) | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AHC2G08DC | 2.0?-?5.5 | CMOS | ± 8 | 3.2 | 60 | 2 | low | -40~125 | 205 | 35.8 | 116 | VSSOP8 |
| 74AHC2G08DP | 2.0?-?5.5 | CMOS | ± 8 | 3.2 | 60 | 2 | low | -40~125 | 218 | 20.9 | 106 | TSSOP8 |
| 74AHCT2G08DC | 4.5?-?5.5 | TTL | ± 8 | 3.6 | 60 | 2 | low | -40~125 | 205 | 35.8 | 116 | VSSOP8 |
| 74AHCT2G08DP | 4.5?-?5.5 | TTL | ± 8 | 3.6 | 60 | 2 | low | -40~125 | 218 | 20.9 | 106 | TSSOP8 |
封裝
| 型號(hào) | 可訂購的器件編號(hào)，（訂購碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74AHC2G08DC | 74AHC2G08DC,125 (935275125125) |
Active | A08 |
VSSOP8 (SOT765-1) |
SOT765-1 | SOT765-1_125 | |
| 74AHC2G08DP | 74AHC2G08DP,125 (935274676125) |
Active | A08 |
TSSOP8 (SOT505-2) |
SOT505-2 | SOT505-2_125 | |
| 74AHCT2G08DC | 74AHCT2G08DC,125 (935275127125) |
Active | C08 |
VSSOP8 (SOT765-1) |
SOT765-1 | SOT765-1_125 | |
| 74AHCT2G08DP | 74AHCT2G08DP,125 (935274677125) |
Active | C08 |
TSSOP8 (SOT505-2) |
SOT505-2 | SOT505-2_125 |
環(huán)境信息
| 型號(hào) | 可訂購的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74AHC2G08DC | 74AHC2G08DC,125 | 74AHC2G08DC |
|
|
| 74AHC2G08DP | 74AHC2G08DP,125 | 74AHC2G08DP |
|
|
| 74AHCT2G08DC | 74AHCT2G08DC,125 | 74AHCT2G08DC |
|
|
| 74AHCT2G08DP | 74AHCT2G08DP,125 | 74AHCT2G08DP |
|
|
文檔 (14)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74AHC_AHCT2G08 | Dual 2-input AND gate | Data sheet | 2023-09-01 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| mna221 | Block diagram: 74AHC08BQ, 74AHC08D, 74AHC08PW, 74AHC2G08DC, 74AHC2G08DP, 74AHC2G08GD, 74AHCT08BQ, 74AHCT08D, 74AHCT08PW, 74AHCT2G08DC, 74AHCT2G08DP, 74AHCT2G08GD, 74AUP1G08GF, 74AUP1G08GM, 74AUP1G08GW, 74HC2G08DC, 74HC2G08DP, 74HC2G08GD, 74HCT2G08DC, 74HCT2G08DP, 74HCT2G08GD, 74LV08D, 74LV08DB, 74LV08N, 74LV08PW, 74LV125D, 74LV125DB, 74LV125N, 74LV125PW | Block diagram | 2009-11-03 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| SOT765-1 | 3D model for products with SOT765-1 package | Design support | 2020-01-22 |
| SOT505-2 | 3D model for products with SOT505-2 package | Design support | 2019-01-18 |
| ahc2g08 | ahc2g08 IBIS model | IBIS model | 2013-04-08 |
| ahct2g08 | ahct2g08 IBIS model | IBIS model | 2013-04-08 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| VSSOP8_SOT765-1_mk | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Marcom graphics | 2017-01-28 |
| SOT765-1 | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Package information | 2022-06-03 |
| SOT505-2 | plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm body | Package information | 2022-06-03 |
| SOT996-2 | plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 3 mm x 2 mm x 0.5 mm body | Package information | 2020-04-21 |
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