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Click here for more information74HCT109DB
Dual JK flip-flop with set and reset; positive-edge-trigger
The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by connecting the J and K inputs together. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
Alternatives
Features and benefits
J and K inputs for easy D-type flip-flop
Toggle flip-flop or "do nothing" mode
Wide supply voltage range:
For 74HC109: from 2.0 V to 6.0 V
For 74HCT109: from 4.5 V to 5.5 V
CMOS low power dissipation
High noise immunity
Input levels:
For 74HC109: CMOS level
For 74HCT109: TTL level
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
74HC109 complies with JEDEC standards:
JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)
74HCT109 complies with JEDEC standard JESD7A (2.0 V to 6.0 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
參數(shù)類型
| 型號 | Package name |
|---|---|
| 74HCT109DB | SSOP16 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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封裝
下表中的所有產(chǎn)品型號均已停產(chǎn) 。
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74HCT109DB | 74HCT109DB,112 (935186320112) |
Obsolete | HCT109 |
SSOP16 (SOT338-1) |
SOT338-1 |
SSOP-TSSOP-VSO-REFLOW
SSOP-TSSOP-VSO-WAVE |
暫無信息 |
| 74HCT109DB,118 (935186320118) |
Obsolete | HCT109 | 暫無信息 |
環(huán)境信息
下表中的所有產(chǎn)品型號均已停產(chǎn) 。
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74HCT109DB | 74HCT109DB,112 | 74HCT109DB |
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| 74HCT109DB | 74HCT109DB,118 | 74HCT109DB |
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Series
文檔 (8)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| AN11044 | Pin FMEA 74HC/74HCT family | Application note | 2019-01-09 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| SSOP16_SOT338-1_mk | plastic, shrink small outline package; 16 leads; 0.65 mm pitch; 6.2 mm x 5.3 mm x 2 mm body | Marcom graphics | 2017-01-28 |
| SOT338-1 | plastic, shrink small outline package; 16 leads; 0.65 mm pitch; 6.2 mm x 5.3 mm x 2 mm body | Package information | 2022-06-20 |
| SSOP-TSSOP-VSO-REFLOW | Footprint for reflow soldering | Reflow soldering | 2009-10-08 |
| HCT_USER_GUIDE | HC/T User Guide | User manual | 1997-10-31 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
Longevity
The Nexperia Longevity Program is aimed to provide our customers information from time to time about the expected time that our products can be ordered. The NLP is reviewed and updated regularly by our Executive Management Team. View our longevity program here.
模型
No documents available
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.