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Click here for more information74LVC1G79GF
Single D-type flip-flop; positive-edge trigger
The 74LVC1G79 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Alternatives
Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
Overvoltage tolerant inputs to 5.5 V
High noise immunity
CMOS low power dissipation
±24 mA output drive (VCC = 3.0 V)
Direct interface with TTL levels
Latch-up performance exceeds 250 mA
IOFF circuitry provides partial Power-down mode operation
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C.
參數(shù)類型
| 型號 | Package name |
|---|---|
| 74LVC1G79GF | XSON6 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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封裝
下表中的所有產品型號均已停產 。
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC1G79GF | 74LVC1G79GF,132 (935282425132) |
Obsolete | VP |
XSON6 (SOT891) |
SOT891 | SOT891_132 |
環(huán)境信息
下表中的所有產品型號均已停產 。
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVC1G79GF | 74LVC1G79GF,132 | 74LVC1G79GF |
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Series
文檔 (12)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74LVC1G79 | Single D-type flip-flop; positive-edge trigger | Data sheet | 2025-09-09 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| AN90063 | Questions about package outline drawings | Application note | 2025-10-22 |
| Nexperia_document_guide_MiniLogic_MicroPak_201808 | MicroPak leadless logic portfolio guide | Brochure | 2018-09-03 |
| SOT891 | 3D model for products with SOT891 package | Design support | 2019-10-03 |
| lvc1g79 | 74LVC1G79 IBIS model | IBIS model | 2014-10-20 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| DFN1010-6_SOT891_mk | plastic, extremely thin small outline package; 6 terminals; 0.55 mm pitch; 1 mm x 1 mm x 0.5 mm body | Marcom graphics | 2017-01-28 |
| SOT891 | plastic, leadless extremely thin small outline package; 6 terminals; 0.35 mm pitch; 1 mm x 1 mm x 0.5 mm body | Package information | 2020-04-21 |
| lvc | lvc Spice model | SPICE model | 2013-05-07 |
| MAR_SOT891 | MAR_SOT891 Topmark | Top marking | 2013-06-03 |
Longevity
The Nexperia Longevity Program is aimed to provide our customers information from time to time about the expected time that our products can be ordered. The NLP is reviewed and updated regularly by our Executive Management Team. View our longevity program here.
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.